By Cicero S. Vaucher
This article describes a conceptual framework for reading the functionality of PLL frequency synthesizers, and provides optimization strategies for different functionality elements. It comprises simple details and in-depth wisdom, generally illustrated with functional layout examples utilized in commercial items.
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Extra info for Architectures for RF Frequency Synthesizers (The Springer International Series in Engineering and Computer Science)
The input signals cause the up and down signals to become active at the same moment. The AND gate reacts to the simultaneous presence of up and down by generating the reset signal for the D-FFs, whereupon up and down become inactive again. We notice that there is no output current from the chargepump in this situation, as (ideally) the current sourced in response to the up signal is perfectly compensated by the current sinked in response to the down signal. This is a desirable behavior for an “in-lock” situation, as the absence of an output signal from the charge-pump avoids spectral purity degradation of the VCO.
Its noise contribution can be designed to be non-dominant, yet at the cost of increased total power dissipation. This consideration is especially important for low-power applications, because the loop filter’s circuitry can become the dominant source of power dissipation . 4 DIMENSIONING OF THE PLL PARAMETERS — BASIC CONCEPTS In practice, PLL frequency synthesizers are never a system of the secondorder,5 as there are additional poles in the loop filter to provide adequate suppression of reference spurious breakthrough signals.
This is the ideal locking position for the loop: there is no current injection into the loop filter, and therefore no degradation of spectral purity performance of the VCO. Phase lock with zero phase error, for all possible output frequencies, requires a loop PLL Building Blocks 39 filter with infinite DC gain . In other words, the loop filter must perform an integration operation on the charge-pump output signal. As the pump output is a node with an ideally infinite output impedance, a simple capacitor suffices to realize the integration function at the loop filter.
Architectures for RF Frequency Synthesizers (The Springer International Series in Engineering and Computer Science) by Cicero S. Vaucher